S3C44B0X Просмотр технического описания (PDF) - Samsung

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S3C44B0X

RISC MICROPROCESSOR

Samsung 

PRODUCT OVERVIEW

S3C44B0X RISC MICROPROCESSOR

SIGNAL DESCRIPTIONS

Table 1-3. S3C44B0X Signal Descriptions

Signal

I/O

Description

BUS CONTROLLER

OM[1:0]

I OM[1:0] sets S3C44B0X in the TEST mode, which is used only at fabrication. Also, it

determines the bus width of nGCS0. The logic level is determined by the pull-up/down

resistor during the RESET cycle.

00:8-bit

01:16-bit

10:32-bit

11:Test mode

ADDR[24:0]

O ADDR[24:0] (Address Bus) outputs the memory address of the corresponding bank .

DATA[31:0]

IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write. The bus width is programmable among 8/16/32-bit.

nGCS[7:0]

nWE

O nGCS[7:0] (General Chip Select) are activated when the address of a memory is within

the address region of each bank. The number of access cycles and the bank size can

be programmed.

O nWE (Write Enable) indicates that the current bus cycle is a write cycle.

nWBE[3:0]

O Write Byte Enable

nBE[3:0]

O Upper Byte/Lower Byte Enable(In case of SRAM)

nOE

O nOE (Output Enable) indicates that the current bus cycle is a read cycle.

nXBREQ

I

nXBACK

O

nWAIT

I

ENDIAN

I

DRAM/SDRAM/SRAM

nRAS[1:0]

O

nCAS[3:0]

O

nSRAS

O

nSCAS

O

nSCS[1:0]

O

DQM[3:0]

O

SCLK

O

SCKE

O

nXBREQ (Bus Hold Request) allows another bus master to request control of the local

bus. BACK active indicates that bus control has been granted.

nXBACK (Bus Hold Acknowledge) indicates that the S3C44B0X has surrendered

control of the local bus to another bus master.

nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current bus

cycle cannot be completed.

It determines whether or not the data type is little endian or big endian. The logic level

is determined by the pull-up/down resistor during the RESET cycle.

0:little endian 1:big endian

Row Address Strobe

Column Address strobe

SDRAM Row Address Strobe

SDRAM Column Address Strobe

SDRAM Chip Select

SDRAM Data Mask

SDRAM Clock

SDRAM Clock Enable

1-18

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