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S-89220A

MINI ANALOG SERIES CMOS COMPARATOR

Seiko Instruments Inc 

Rev.2.1_00

MINI ANALOG SERIES CMOS COMPARATOR

S-89210A/89220A

„ Measurement Circuit

1. Power supply voltage rejection ratio, input offset voltage

VDD

y Power supply voltage rejection ratio (PSRR)

Input offset voltage (VIO)

-

+

VDD / 2

VIN

Figure 6

VOUT

The input offset voltage (VIO) is defined as VIN − VDD/2

when VOUT is changed by changing VIN to VDD/2 level.

The power supply voltage rejection ratio (PSRR) can be

calculated by following expression, with the value of VIO

measured at each VDD.

Measurement conditions:

When VDD = 1.8 V: VDD = VDD1, VIO = VIO1

When VDD = 5.0 V: VDD = VDD2, VIO = VIO2

PSRR = 20 log

VDD1 − VDD2

VIO1 − VIO2

2. Common-mode input signal rejection ratio, common-mode input voltage range

VDD

y Common-mode input signal rejection ratio (CMRR)

The common-mode input signal rejection ratio (CMRR)

can be calculated by the following expression, with the

offset voltage (VIO) set as VIN1 minus VIN2 after VOUT is

changed by changing VIN1.

-

+

VOUT

Measurement conditions:

When VIN2 = VCMR (max.): VIN2 = VINH, VIO = VIO1

When VIN2 = VDD/2: VIN2 = VINL, VIO = VIO2

VIN1

VIN2

CMRR = 20 log

VINH − VINL

VIO1− VIO2

y Common-mode input voltage range (VCMR)

The common-mode input voltage range is the range

of VIN2 in which VOUT satisfies the common-mode input

signal rejection ratio specifications.

Figure 7

Seiko Instruments Inc.

7

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