M80C186EB-13 Просмотр технического описания (PDF) - Intel

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M80C186EB-13

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186EB

ERRATA

The current stepping (B step) of the M80C186EB

has the following known functional anomaly

An internal problem with the interrupt controller

may prevent an acknowledge cycle from occur-

ring on the INTA1 line after an interrupt on INT1

This error only occurs when INT1 is configured in

cascaded mode and a higher priority interrupt ex-

ists

Problem

An interrupt acknowledge for INT1 is not generat-

ed on INTA1 in some conditions

Condition

Another interrupt of higher priority occurs after

the decision is made to service Interrupt 1 but

before the expected acknowledge cycle on

INTA1

Configuration

1 Master mode

2 INT1 is in cascade mode and is enabled

3 An interrupt of higher priority than INT1 is en-

abled (i e DMA timers serial ports INT

lines)

Workaround

There are only two possible situations that might

cause this problem These with their correspond-

ing workarounds are described in the table below

Condition

1 Only INT1 is

configured in cascade

mode and is also a

lower priority than

another interrupt

2 INT1 and INT0 are

both in cascade mode

and INT1 is of lower

priority than another

interrupt

Workaround

Use INT0 in cascaded

mode instead or

make INT1 the highest

priority interrupt

Change the priority of

INT1 to the highest

priority of all interrupts

REVISION HISTORY

The first revision of this data sheet (271214-001) in-

dicated only 8 MHz and 13 MHz availability The

M80C186EB will also be available in a 16 MHz ver-

sion The cover and various other locations in the

data sheet reflect the additional product speed offer-

ing

The following list reflects the changes made be-

tween the -001 version and this -002 version of the

M80C186EB data sheet

1 Operating Conditions section updated to reflect

16 MHz Input clock frequency limits

2 DC Specifications section Added notes regard-

ing untested values added changed input leak-

age current and input current symbols and val-

ues added 16 MHz ICC IID and IPD values

3 AC Specifications section Added full 16 MHz AC

Characteristics added note about untested val-

ues and reduced minimum output delays (TCHOV

and TCLOV) for all speeds

4 Modified Errata section to reflect B-step known

errata (INT1 acknowledge anomaly)

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