M80C186EB Просмотр технического описания (PDF) - Intel

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M80C186EB

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186EB

REGISTER BIT SUMMARY

Figures 27 through 34 present the bit definition of

each register that is active (not reserved) in the Pe-

ripheral Control Block (PCB) Each register can be

thought to occupy one word (16-bits) of either mem-

ory or I O space although not all bits in the register

necessarily have a function A register bit is not

guaranteed to return a specific logic value if an ‘‘X’’

appears for the bit definition (i e if a zero was writ-

ten to the register bit it may not be returned as a

zero when read) Furthermore a 0 must be written to

any bit that is indicated by an ‘‘X’’ to ensure compati-

bility with future products or potential product chang-

es

Not all defined register bits can be read and or

written although most registers are read write

Some registers like the P1DIR register exist but do

not have any effect on the operation of the

M80C186EB For example the Port1 pins are output

only and cannot be changed by programming the

P1DIR register However the P1DIR register can still

be read and written which allows the P1DIR regis-

ter to be used as a temporary 8-bit data register

Reads and writes to any of the PCB registers will

cause a bus cycle to be run externally however

none of the chip selects will go active (even if they

overlap the PCB address range) Data read back

from the AD15 0 bus is ignored and all cycles will

take zero wait states (except accesses to the Timer

Counter registers which take one wait state due to

internal synchronization)

Figures 27 and 28 present the registers associated

with the Interrupt Control Unit (ICU) A write to the

MASK (08H) register will also effect the correspond-

ing MSK bit in each of the control registers (e g

setting the TMR bit in the MASK register will also set

the MSK bit in the TMRCON register)

The Timer Counter Unit registers are presented in

Figure 29 The compare and count registers are not

initialized after reset and must be set correctly dur-

ing initialization to ensure the timer operates correct-

ly the first time it is enabled

Figure 30 presents the I O Port Unit (IPU) registers

Only PD6 and PD7 or of the P2DIR register have any

effect on the direction of the port pins (P2 6 and

P2 7 respectively) The unused bits of P2DIR and all

the bits of P1DIR can be thought of having latches

that can be read and written The two PxLTCH regis-

ters have all 8-bits implemented however only

those port pins which can function as outputs actual-

ly use the value programmed into the latch Other-

wise (like the P1DIR register) the registers can be

thought of being an 8-bit data register

Figure 31 presents the register bit definitions of the

Serial Communications Unit (SCU) The transmit and

receive buffer registers are both readable and write-

able Note that a read from SxSTS register will clear

all of the status information (except for CTS which

actually is derived from the pin itself)

The Chip-Select Unit (CSU) registers are presented

in Figure 32 and the Refresh Control Unit (RCU) reg-

isters are presented in Figure 33 The RFADDR reg-

ister will indicate the current refresh address when

read and a write to the register will change the next

refresh address generated

Figure 34 presents the PWRCON register and

STEPID register The STEPID register contains a

stepping identifier that may or may not change any

time there is a change to the M80C186EB silicon

die The STEPID is for Intel use and can change at

any time

44

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