M80C186EB-8 Просмотр технического описания (PDF) - Intel

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M80C186EB-8

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186EB

Other timer programming options include

 All three timers can be set to halt or continue

after a compare match

 Timers 0 and 1 can be reset or retriggered using

their respective input pins

 TCU registers can be read or written at any time

SERIAL COMMUNICATIONS UNIT

The Serial Control Unit (SCU) of the M80C186EB

contains two independent channels Each channel is

identical in operation except that only channel 0 is

supported by the integrated interrupt controller

(channel 1 has an external interrupt pin) Each

channel has its own baud rate generator that is in-

dependent of the Timer Counter Unit and can be

internally or externally clocked at up to one half the

M80C186EB operating frequency

Each serial channel supports one synchronous and

four asynchronous modes of operation and is com-

patible with the serial ports of the MCS -51 and

MCS -96 family of products Data field length can

be 7- 8- or 9-bits with optional odd or even parity

(generated and checked) and one stop bit (generat-

ed and checked) The 9-bit mode has an optional

‘‘addressing’’ feature to simplify interprocessor com-

munication Each serial port is doubled buffered in

both transmit and receive operation (data can be

read or written to a buffer register while data is shift-

ed into or out of a shifting register respectively)

A Clear-To-Send input pin can be programmed to

prevent data transmission if the pin is sampled inac-

tive Serial channel 0 is supported by the integrated

interrupt controller providing separate receive and

transmit vector types Serial channel 1 has an exter-

nal interrupt pin which OR’s the receive and transmit

interrupts This external interrupt pin can be routed

to either the external pins of the ICU the NMI pin or

any other external system interrupt controller Status

bits are provided to allow polling of the serial chan-

nels if interrupts are not desired

Independent baud rate generators are provided for

each of the serial channels For the asynchronous

modes the generator supplies an 8x baud clock to

both the receive and transmit register logic A 1x

baud clock is provided in the synchronous mode

Additional features of the SCU include

 Framing error receive buffer overrun error and

parity error detection

 Break detect

 Break send

CHIP-SELECT UNIT

The M80C186EB Chip-Select Unit (CSU) integrates

logic which provides up to ten programmable chip-

selects to access both memories and peripherals In

addition each chip-select can be programmed to

automatically insert additional clocks (wait-states)

into the current bus cycle and automatically termi-

nate a bus cycle independent of the condition of the

READY input pin

Each of the chip-selects can be programmed to go

active for either memory or I O accesses UCS is

the only chip-select that is active after a reset and is

enabled for memory addresses in the range

0FFC00H to 0FFFFFH (this allows a boot-ROM to

be accessed using UCS) Every chip-select has a

programmable start and stop register that defines

the active region for the chip-select and the ready

characteristics for the region

The start and stop address fields are 10 bits in

length and are matched against the upper 10 bits of

either the memory or I O address A 10-bit compare

results in a granularity of 1 Kbytes for memory ac-

cesses and 64 bytes for I O accesses Each chip

select can be disabled by programming its start ad-

dress greater than its stop address or by clearing its

enable bit

Each chip-select can be programmed to automati-

cally insert wait-states and to control whether the

external READY input is to be ignored or used The

M80C186EB bus controller will wait the programmed

number of wait-states before the external READY

pin can be used to extend or terminate the bus cy-

cle

Overlapping of chip-selects is allowed However

each one that overlaps will go active If any overlap-

ping chip-select has been programmed to use exter-

nal ready the bus control unit will insert the least

amount of programmed wait-states programmed be-

fore the external ready pin is used If all overlapped

chip-selects ignore external ready the bus controller

will insert the maximum number of programmed

wait-states Any chip-select that overlaps the Periph-

eral Control Block (PCB) will not go active for that

portion of the address range allocated to the PCB

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