PSD853F5V90UI Просмотр технического описания (PDF) - STMicroelectronics

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PSD853F5V90UI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

JTAG Port

In-System Programming (ISP) can be performed

through the JTAG signals on Port C. This serial in-

terface allows complete programming of the entire

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR, TDI, TDO) can be multiplexed with

other functions on Port C. Table 4 indicates the

JTAG pin assignments.

In-System Programming (ISP)

Using the JTAG signals on Port C, the entire PSD

device can be programmed or erased without the

use of the MCU. The primary Flash memory can

also be programmed in-system by the MCU exe-

cuting the programming algorithms out of the sec-

ondary memory, or SRAM. The secondary

memory can be programmed the same way by ex-

ecuting out of the primary Flash memory. The PLD

or other PSD Configuration blocks can be pro-

grammed through the JTAG port or a device pro-

grammer. Table 5 indicates which programming

methods can program different functional blocks

of the PSD.

Power Management Unit (PMU)

The Power Management Unit (PMU) gives the

user control of the power consumption on selected

functional blocks based on system requirements.

The PMU includes an Automatic Power-down

(APD) Unit that turns off device functions during

MCU inactivity. The APD Unit has a Power-down

mode that helps reduce power consumption.

The PSD also has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to '0' and the CPLD latches its outputs and

goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the

MCU to block signals from entering the CPLD to

reduce power consumption. Please see the sec-

tion entitled POWER MANAGEMENT, page 62 for

more details.

Table 4. JTAG SIgnals on Port C

Port C Pins

JTAG Signal

PC0

TMS

PC1

TCK

PC3

TSTAT

PC4

TERR

PC5

TDI

PC6

TDO

Table 5. Methods of Programming Different Functional Blocks of the PSD

Functional Block

JTAG Programming Device Programmer

IAP

Primary Flash Memory

Yes

Yes

Yes

Secondary Flash Memory

Yes

Yes

Yes

PLD Array (DPLD and CPLD)

Yes

Yes

No

PSD Configuration

Yes

Yes

No

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