PFM19030 Просмотр технического описания (PDF) - Cree, Inc
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PFM19030 Datasheet PDF : 15 Pages
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PFM19030
Test Fixture Schematic
GND
+27 V
+27 V
OpAmp
J2 Not Used for Demo Fixture
J1
8
7
6
5
4
3
2
1
J2
8
7
6
5
4
3
2
1
C31
C37
R12
R11
C32
R16
R13
4 - 5 U1
LM8261
C42
C40
R14 3 + 2 1
C33
R19
R20
R15
R17
R18
S1
D1
RZ_FS1
RZ_FS2
C34
C36
R32
R31
C41
R36 U2
R33 4 5
-
R34
3
+LM8261
2
R37 C35
R39
R35
R38
C43
R40
S2
D2
C28
C27
C24
C22
C20
C23
C21
C19
C2
RF
Out
C1
RF
OUT
C26 C12 C11 C10
C25
C14
C18 C17 C16 C15
PFM19030SM
Drain 1
Sense D2
Gate 2
Sense D1
RF IN
C9
C8
C7
R1
C3
R2
RF
Input
C4
C6
C5
See the following pages for the parts list and a description of the principle of operation. Note that an
alternative, less complex bias scheme is provided later in this applications note. The advantage of the above
bias design is that bias currents are set by the RF-to-Sense FET ratios, and once the optimum bias circuit
resistor (potentiometer) values are established, the circuit can stay fixed for multiple modules (thus
eliminating module-specific bias alignment). Additionally, aging effects are minimized because of the
Page 12 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
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