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P80C54UFBB

80C51 8-bit microcontroller family 8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz)

Philips Electronics 

Philips Semiconductors

80C51 8-bit microcontroller family

8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33MHz)

Product specification

8XC52/54/58/80C32

8XC51FA/FB/FC/80C51FA

8XC51RA+/RB+/RC+/RD+/80C51RA+

Table 2.

SYMBOL

PSW*

RACAP2H#

RACAP2L#

8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued)

DESCRIPTION

DIRECT

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

Program Status Word

D0H

CY

AC

F0

RS1 RS0

OV

–

P

Timer 2 Capture High

Timer 2 Capture Low

CBH

CAH

RESET

VALUE

000000x0B

00H

00H

SADDR# Slave Address

A9H

00H

SADEN# Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

SCON*

SP

Serial Control

Stack Pointer

TCON*

Timer Control

99H

9F

9E

9D

9C

9B

9A

99

98H SM0/FE SM1 SM2 REN

TB8

RB8

TI

81H

8F

8E

8D

8C

8B

8A

89

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

xxxxxxxxB

98

RI 00H

07H

88

IT0 00H

T2CON*

T2MOD#

Timer 2 Control

Timer 2 Mode Control

TH0

TH1

TH2#

TL0

TL1

TL2#

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2

C8H

C9H

8CH

8DH

CDH

8AH

8BH

CCH

CF

CE

CD

CC

CB

CA

C9

C8

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H

–

–

–

–

–

– T2OE DCEN xxxxxx00B

00H

00H

00H

00H

00H

00H

TMOD

Timer Mode

89H GATE C/T

M1

M0

GATE C/T

M1

M0 00H

WDTRST HDW Watchdog

0A6H

Timer Reset (RX+ only)

* SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

– Reserved bits.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-on reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-on, the voltage on

VCC and RST must come up at the same time for a proper start-up.

Ports 1, 2, and 3 will asynchronously be driven to their reset

condition when a voltage above VIH1 (min.) is applied to RESET.

1999 Apr 01

12

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