MX26L6420TC-90 Просмотр технического описания (PDF) - Macronix International

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MX26L6420TC-90

64M-BIT [4M x 16] CMOS MULTIPLE-TIME-PROGRAMMABLE EPROM

Macronix International 

MX26L6420

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host sys-tem

whether an Automatic Algorithm is in progress or com-

pleted. Data Polling is valid after the rising edge of the

final WE pulse in the program or erase command se-

quence.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7. This Q7 status also applies to programming dur-

ing Er ase Suspend. When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7. The system must provide the program

address to read valid status information on Q7.

During the Automatic Erase algorithm, Data Polling pro-

duces a "0" on Q7. When the Automatic Erase algo-

rithm is complete. Data Polling produces a "1" on Q7.

This is analogous to the complement/true datum output

described for the Automatic Program algorithm: the erase

function changes all the bits to "1" prior to this, the de-

vice outputs the "complement,” or "0".

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchr onously with Q0-Q6 while Output En-

able (OE) is asserted low.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data Polling and Toggle Bit are the

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during chip erase opera-

tion, it specifies that device is bad and it may not be

reused. Write the Reset command sequence to the de-

vice, and then execute program or erase command se-

quence. This allows the system to continue to use the

other active sectors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad.

If this time-out condition occurs during the word program-

ming operation, the word is bad and maynot be reused,

(other word are still functional and can be reused).

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete. Toggle

Bit I may be read at any address, and is valid after the

rising edge of the final WE or CE, whichever happens

first pulse in the command sequence(prior to the pro-

gram or erase operation).

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE or CE to con-

trol the read cycles. When the operation is complete, Q6

stops toggling.

Table 6 shows the outputs for Toggle Bit I on Q6.

P/N:PM0823

REV. 0.5, JAN. 29, 2002

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