MX25L4005 Просмотр технического описания (PDF) - Macronix International
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MX25L4005 Datasheet PDF : 41 Pages
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MX25L4005
Table 6. AC CHARACTERISTICS (Temperature = -40° C to 85° C for Industrial grade, Temperature =
0° C to 70° C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter
Min. Typ. Max. Unit
fSCLK fC Clock Frequency for the following instructions:
D.C.
70 MHz
FAST_READ, PP, SE, BE, CE, DP, RES,RDP
(Condition:15pF)
WREN, WRDI, RDID, RDSR, WRSR
66 MHz
(Condition:30pF)
fRSCLK fR Clock Frequency for READ instructions
D.C.
33 MHz
tCH(1)
tCLH Clock High Time
7
ns
tCL(1)
tCLL Clock Low Time
7
ns
tCLCH(2)
Clock Rise Time (3) (peak to peak)
0.1
V/ns
tCHCL(2)
Clock Fall Time (3) (peak to peak)
0.1
V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
5
ns
tCHSL
CS# Not Active Hold Time (relative to SCLK)
5
ns
tDVCH tDSU Data In Setup Time
2
ns
tCHDX tDH Data In Hold Time
5
ns
tCHSH
CS# Active Hold Time (relative to SCLK)
5
ns
tSHCH
CS# Not Active Setup Time (relative to SCLK)
5
ns
tSHSL tCSH CS# Deselect Time
100
ns
tSHQZ(2) tDIS Output Disable Time
6
ns
tCLQV tV Clock Low to Output Valid @33MHz 30pF
8
ns
@70MHz 15pF or @66MHz 30pF
6
ns
tCLQX tHO Output Hold Time
0
ns
tHLCH
HOLD# Setup Time (relative to SCLK)
5
ns
tCHHH
HOLD# Hold Time (relative to SCLK)
5
ns
tHHCH
HOLD Setup Time (relative to SCLK)
5
ns
tCHHL
HOLD Hold Time (relative to SCLK)
5
ns
tHHQX(2) tLZ HOLD to Output Low-Z
6
ns
tHLQZ(2) tHZ HOLD# to Output High-Z
6
ns
tWHSL(4)
Write Protect Setup Time
20
ns
tSHWL(4)
Write Protect Hold Time
100
ns
tDP(2)
CS# High to Deep Power-down Mode
3
us
tRES1(2)
CS# High to Standby Mode without Electronic Signature Read
3
us
tRES2(2)
CS# High to Standby Mode with Electronic Signature Read
1.8 us
tW
Write Status Register Cycle Time
5
15
ms
tPP
Page Program Cycle Time
1.4 5
ms
tSE
Sector Erase Cycle Time
60 120 ms
tBE
Block Erase Cycle Time
1
2
s
tCE
Chip Erase Cycle Time
3.5 7.5
s
Note:
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 3.
P/N: PM1236
REV. 1.1, SEP. 30, 2005
21
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