MU9C1480A Просмотр технического описания (PDF) - MUSIC Semiconductors
Номер в каталоге
Компоненты Описание
производитель
MU9C1480A Datasheet PDF : 32 Pages
| |||
Instruction Set Summary
LANCAM A/L series (not recommended for new designs)
Instruction: Data Move (continued)
Operation
Mnemonic
Op-Code
Mask Register 2 from:
Comparand Register
MOV MR2,CR
0310H
Mask Register 1
MOV MR2,MR1
0311H
No Operation
NOP
0312H
Memory at Address Reg.
MOV MR2,[AR]
0314H
Memory at Address
MOV MR2,aaaH
0B14H
Mem. at Highest-Prio. Match
MOV MR2,HM
0315H
Memory at Address Register, No Change to Validity bits, from:
Comparand Register
MOV [AR],CR
0320H
Masked by MR1
MOV [AR],CR[MR1]
0360H
Masked by MR2
MOV [AR],CR[MR2]
03A0H
Mask Register 1
MOV [AR],MR1
0321H
Mask Register 2
MOV [AR],MR2
0322H
Memory at Address Register, Location set Valid, from:
Comparand Register
MOV [AR],CR,V
0324H
Masked by MR1
MOV [AR],CR[MR1],V
0364H
Masked by MR2
MOV [AR],CR[MR2],V
03A4H
Mask Register 1
MOV [AR],MR1,V
0325H
Mask Register 2
MOV [AR],MR2,V
0326H
Memory at Address, No Change to Validity bits, from:
Comparand Register
MOV aaaH0,CR
0B20H
Masked by MR1
MOV aaaH,CR[MR1]
0B60H
Masked by MR2
MOV aaaH,CR[MR2]
0BA0H
Mask Register 1
MOV aaaH,MR1
0B21H
Mask Register 2
MOV aaaH,MR2
0B22H
Memory at Address, Location set Valid, from:
Comparand Register
MOV aaaH,CR,V
0B24H
Masked by MR1
MOV aaaH,CR[MR1],V
0B64H
Masked by MR2
MOV aaaH,CR[MR2],V
0BA4H
Mask Register 1
MOV aaaH,MR1,V
0B25H
Mask Register 2
MOV aaaH,MR2,V
0B26H
Memory at Highest-Priority Match, No Change to Validity bits, from:
Comparand Register
MOV HM,CR
0328H
Masked by MR1
MOV HM,CR[MR1]
0368H
Masked by MR2
MOV HM,CR[MR2]
03A8H
Mask Register 1
MOV HM,MR1
0329H
Mask Register 2
MOV HM,MR2
032AH
Memory at Highest-Priority Match, Location set Valid, from:
Comparand Register
MOV HM,CR,V
032CH
Masked by MR1
MOV HM,CR[MR1],V
036CH
Masked by MR2
MOV HM,CR[MR2],V
03ACH
Mask Register 1
MOV HM,MR1,V
032DH
Mask Register 2
MOV HM,MR2,V
032EH
Memory at Next Free Address, No Change to Validity bits, from:
Comparand Register
MOV NF,CR
0330H
Masked by MR1
MOV NF,CR[MR1]
0370H
Masked by MR2
MOV NF,CR[MR2]
03B0H
Mask Register 1
MOV NF,MR1
0331H
Mask Register 2
MOV NF,MR2
0332H
Memory at Next Free Address, Location set Valid, from:
Comparand Register
MOV NF,CR,V
0334H
Masked by MR1
MOV NF,CR[MR1],V
0374H
Masked by MR2
MOV NF,CR[MR2],V
03B4H
Mask Register 1
MOV NF,MR1,V
0335H
Mask Register 2
MOV NF,MR2,V
0336H
Instruction: Validity Bit Control
Operation
Mnemonic
Set Validity bits at Address Register
Set Valid
VBC [AR],V
Set Empty
VBC [AR],E
Set Skip
VBC [AR],S
Set Random Access
VBC [AR],R
Set Validity bits at Address
Set Valid
VBC aaaH,V
Set Empty
VBC aaaH,E
Set Skip
VBC aaaH,S
Set Random Access
VBC aaaH,R
Set Validity bits at Highest-Priority Match
Set Valid
VBC HM,V
Set Empty
VBC HM,E
Set Skip
VBC HM,S
Set Random Access
VBC HM,R
Set Validity bits at All Matching Locations
Set Valid
VBC ALM,V
Set Empty
VBC ALM,E
Set Skip
VBC ALM,S
Set Random Access
VBC ALM,R
Instruction: Compare
Operation
Compare Valid Locations
Compare Empty Locations
Compare Skipped Locations
Comp. Random Access Locations
Mnemonic
CMP V
CMP E
CMP S
CMP R
Instruction: Special Instructions
Operation
Shift Comparand Right
Shift Comparand Left
Shift Mask Register 2 Right
Shift Mask Register 2 Left
Select Foreground Registers
Select Background Registers
Reset Seg. Cont. Reg. to Initial Val.
Mnemonic
SFT CR, R
SFT CR, L
SFT M2, R
SFT M2, L
SFR
SBR
RSC
Instruction: Miscellaneous
Operation
No Operation
Set Full Flag
Mnemonic
NOP
SFF
Op-Code
0424H
0425H
0426H
0427H
0C24H
0C25H
0C26H
0C27H
042CH
042DH
042EH
042FH
043CH
043DH
043EH
043FH
Op-Code
0504H
0505H
0506H
0507H
Op-Code
0600H
0601H
0610H
0611H
0618H
0619H
061AH
Op-Code
0300H
0700H
Rev. 1
21
Share Link: 