MTL004 Просмотр технического описания (PDF) - Myson Century Inc
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MTL004 Datasheet PDF : 54 Pages
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MYSON
TECHNOLOGY
MTL004
(Rev. 0.95)
3.3.1 Display Timing Generation
Because of no frame buffer, output displaying timing is locked by input timing and output frame rate is equal
to input frame rate. Users must program output timing and lock position to make sure that line buffer will not
overflow or underflow. MTL004 can automatically calculate Display Horizontal Total count to make the output
timing calculation easier. MTL004 also provides line buffer overflow/underflow status for calibrating lock
position.
Input Frame
X
Output Frame
X: lock position
Fig. 3.2.2 Display Timing modes
3.3.2 OSD Overlay
MTL004 allows the integration of overlay data with the scaled output pixel stream. It provides a fully
compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD
device. MTL004 receives OSD Enable, OSD Red, OSD Green, OSD Blue, and OSD Intensity from external
OSD device.
3.3.3 RGB Output Format
MTL004 output interface consists of two pixel ports, each containing Red, Green, and Blue color information
with a resolution of 6/8 bits per color. These two ports are PORT1 and PORT2 respectively.
The control signals for the output port are display horizontal sync signal (DHSYNC), display vertical sync
signal (DVSYNC) and display data enable signal (DDEN).
All the signals mentioned above are synchronous to the output clock. The output timing relative to the active
edge of the output clock is programmable.
There are two RGB output formats:
¨ Single Pixel Mode
Is designed to support TFT panels with single pixel input. Only PORT1 is active. The frequency of DCLK is
equal to internal display clock.
¨ Dual Pixel Mode
Is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at
PORT1, with the second at PORT2.
Revision 0.95
- 11 -
2000/06/14
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