MAX9206EAI/V Просмотр технического описания (PDF) - Maxim Integrated

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MAX9206EAI/V

10-Bit Bus LVDS Deserializers

Maxim Integrated 

10-Bit Bus LVDS Deserializers

Test Circuits/Timing Diagrams (continued)

PWRDN

REFCLK

RI

LOCK HIGH-Z

RCLK

ROUT_

tDSR1 ≤ (2048 + 42)tRFCP

tRFCP

tZHLK

SYNC PATTERNS

111111

000000

HIGH-Z

HIGH-Z

2048 x tRFCP

≤42 x tRFCP

Figure 7. PLL Lock Time from PWRDN

DATA

tDD

tRCP

SYNC

DATA

RCLK_R/F = LOW

DON'T CARE

HIGH-Z

HIGH-Z

tHZR OR tLZR

HIGH-Z

REFCLK

RI

tRFCP

LOCK

RCLK

ROUT_

SYNC PATTERNS

111111

000000

tDSR2 ≤42tRFCP

Figure 8. Deserializer PLL Lock Time from Sync Patterns

DATA

tDD

SYNC

tRCP

DATA

RCLK_R/F = LOW

DATA DATA

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