MAX9206EAI/V Просмотр технического описания (PDF) - Maxim Integrated
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MAX9206EAI/V Datasheet PDF : 12 Pages
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10-Bit Bus LVDS Deserializers
PIN
1, 12, 13
2
3
4, 11
5
6
7
8
9
10
14, 20,
22
15–19,
24–28
21, 23
NAME
AGND
RCLK_R/F
REFCLK
AVCC
RI+
RI-
PWRDN
REN
RCLK
LOCK
DGND
ROUT9–
ROUT0
DVCC
Pin Description
FUNCTION
Analog Ground
Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe
ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of
RCLK.
PLL Reference Clock. LVTTL/LVCMOS level input.
Analog Power Supply. Bypass AVCC with a 0.1µF and a 0.001µF capacitor to AGND.
Serial Data Input. Noninverting BLVDS differential input.
Serial Data Input. Inverting BLVDS differential input.
Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK,
and RCLK in high impedance.
Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high
impedance. LOCK remains active, indicating the status of the serial input.
Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_.
Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency
and phase lock to the serial input, and the framing bits have been identified.
Digital Ground
Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe
edge of RCLK after LOCK goes low.
Digital Power Supply. Bypass DVCC with a 0.1µF and a 0.001µF capacitor to DGND.
Test Circuits/Timing Diagrams
START
START
START
BIT
BIT
END
END BIT
RI
0 1 2 3 4 5 6 7 8 9 BIT
0 1 2 3 4 5 6 7 8 9 BIT
012
TDD
RCLK
ODD
ROUT
RCLK_R/F = HIGH
EVEN
ROUT
Figure 1. Worst-Case ICC Test Pattern
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