MAX6469TA15BD3(2003) Просмотр технического описания (PDF) - Maxim Integrated

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MAX6469TA15BD3
(Rev.:2003)

300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit

Maxim Integrated 

300mA LDO Linear Regulators with Internal

Microprocessor Reset Circuit

Power Dissipation Consideration

For the SOT23 package, any pin except the SET pin

can be used as a heatsink. If the SET pin is used as a

heatsink, excessive parasitic capacitance can affect

stability. For the QFN package, the exposed metal pad

on the back side of a package connects to GND of the

chip. This metal pad can be used as a heatsink.

UCSP Consideration

For general UCSP package information and PC layout

considerations, refer to Maxim Application Note: Wafer-

Level Chip-Scale Package.

UCSP Reliability

The chip-scale package (UCSP) represents a unique

packaging form factor that might not perform equally to

a packaged product through traditional mechanical

reliability tests. CSP reliability is integrally linked to the

user’s assembly methods, circuit-board material, and

usage environment. The user should closely review

these areas when considering a CSP package.

Performance through operating life test and moisture

resistance remains uncompromised, because it is pri-

marily determined by the wafer-fabrication process.

Mechanical stress performance is a greater considera-

tion for a CSP package. CSPs are attached through

direct solder contact to the user’s PC board, forgoing

the inherent stress relief of a packaged product’s lead

frame. Solder-joint contact integrity must be considered.

Information on Maxim’s qualification plan, test data, and

recommendations are detailed in the UCSP application

note on Maxim’s website at www.maxim-ic.com.

Table 1. Output Voltage Suffix Guide

SUFFIX

15

16

17

18

19

20

21

22

23

24

25

26

27

28

285

29

30

31

32

33

OUTPUT

VOLTAGE (V)

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.85

2.9

3.0

3.1

3.2

3.3

Note: Factory-trimmed custom output voltages may be avail-

able; contact factory for availability.

Table 2. Reset Threshold Accuracy Guide

SUFFIX

A

B

VOUT RESET

TOLERANCE (%)

-7.5

-12.5

Table 3. Reset Timeout Delay Guide

SUFFIX

D1

D2

D3

D4

MINIMUM RESET

TIMEOUT PERIOD (ms)

2.5

20

150

1200

12 ______________________________________________________________________________________

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