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MAX3882AETX

2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier

Maxim Integrated 

2.488Gbps 1:4 Demultiplexer with Clock and

Data Recovery and Limiting Amplifier

Input Amplifier

The SDI inputs of the MAX3882A accept serial NRZ

data at 2.488Gbps with 10mVP-P to 1600mVP-P ampli-

tude. The input sensitivity is 10mVP-P, at which the jitter

tolerance is met for a BER of 10-10 when the threshold

adjust is not used. The input sensitivity is as low as

4mVP-P for a BER of 10-10. The MAX3882A is designed

to directly interface with a transimpedance amplifier

(MAX3277).

For applications when vertical threshold adjustment is

needed, the MAX3882A can be connected to the out-

put of an AGC amplifier (MAX3861). Here, the input

voltage range is 50mVP-P to 600mVP-P. See the Design

Procedure section for decision threshold adjust.

Phase Detector

The phase detector in the MAX3882A produces a volt-

age proportional to the phase difference between the

incoming data and the internal clock. Because of its

feedback nature, the PLL drives the error voltage to

zero, aligning the recovered clock to the center of the

incoming data eye for retiming.

Frequency Detector

The digital frequency detector (FD) acquires frequency

lock without using an external reference clock. The fre-

quency difference between the received data and the

VCO clock is derived by sampling the in-phase and

quadrature VCO outputs on both edges of the data

input signal. Depending on the polarity of the frequency

difference, the FD drives the VCO until the frequency

difference is reduced to zero. Once frequency acquisi-

tion is complete, the FD returns to a neutral state. False

locking is eliminated by this digital frequency detector.

Loop Filter and VCO

The fully integrated PLL has a second-order transfer

function, with a loop bandwidth (fL) fixed at 1.7MHz. An

external capacitor between VCC_VCO and FIL sets the

damping of the PLL. All jitter specifications are based

on the CFIL capacitor being 0.068µF. Note that the PLL

jitter transfer bandwidth does not change as the exter-

nal capacitor changes, but the jitter peaking, acquisi-

tion time, and loop stability are affected.

For an overdamped system (fZ/fL) < 0.25, the jitter

peaking (JP) of a second-order system can be approxi-

mated by:

JP = 20log(1 + fZ/fL)

The PLL zero frequency (fZ) is a function of the external

capacitor (CFIL) and can be approximated according to:

fZ = 1/2π(650)CFIL

Figures 6 and 7 show the open-loop and closed-loop

transfer functions. The PLL acquisition time is also

directly proportional to the external capacitor CFIL.

Loss-of-Lock Monitor

The LOL output indicates a PLL lock failure, either due

to excessive jitter present at data input or due to loss of

input data. In the case of loss of input data, the LOL

indicates a loss-of-signal condition. The LOL output is

asserted low when the PLL loses lock.

Output LVDS Interface: PD, PCLK

The MAX3882A’s clock and data outputs are LVDS

compatible to minimize power dissipation, speed tran-

sition time, and improve noise immunity. These outputs

comply with the IEEE LVDS specification. The differen-

tial output signal magnitude is 250mV to 400mV.

Design Procedure

The MAX3882A provides a differential output clock

(PCLK). Table 1 shows the pin configuration for choos-

ing the type of operation mode.

Decision Threshold Adjust

Decision threshold adjust is available for WDM applica-

tions where optical amplifiers are used, generating

spontaneous optical noise at data logic high. The deci-

sion threshold adjust range is ±170mV. Use the provid-

ed 2.2V bandgap reference VREF pin or an outside

source, such as an output from a DAC to control the

Table 1. Operation Modes

FREFSET

LREF

SIS

X

1

0

X

1

1

1

0

X

0

0

X

OPERATION MODE DESCRIPTION

Normal operation: PLL locked to data input at 2.488Gbps

System loopback: PLL lock frequency at 2.488Gbps

Clock holdover: PLL locked to reference frequency at 155MHz

Clock holdover: PLL locked to reference frequency at 622MHz

8 _______________________________________________________________________________________

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