USB 2.0 Full-Speed Transceiver with UART
Multiplexing Mode
Timing Diagrams
TX
50%
tPLH_TUART
90%
D-
50%
10%
tFR_TUART
50%
tPHL_TUART
90%
50%
10%
tFF_TUART
D+
50%
tPLH_RUART
90%
RX
50%
10%
tFR_RUART
Figure 13. UART Transmitter Timing
Figure 14. UART Receiver Timing
Power Sequencing
There are no power-sequencing requirements for VL,
VUART, and VBUS.
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit-
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile, as well as the latest
information on reliability testing results, refer to
the Application Note UCSP- A Wafer-Level Chip-
Scale Package available on Maxim’s website at
www.maxim-ic.com/ucsp.
50%
tPHL_RUART
90%
50%
10%
tFF_RUART
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