M25P05-VMN6T Просмотр технического описания (PDF) - STMicroelectronics

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M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

M25P05

Table 6. Protection Modes

W SRWD

Signal Bit

Mode

Write Protection of the

Status Register

Memory Content

Protected Area1

Unprotected Area1

1

0

Status Register is

Writable (if the WREN

0

0

Software instruction has set the

Protected against Page Ready to accept Page

Protected WEL bit)

Program and Sector

Program and Sector

(SPM) The values in the BP1

Erase

Erase instructions

1

1

and BP0 bits can be

changed

Status Register is

Hardware Hardware write protected Protected against Page Ready to accept Page

0

1

Protected The values in the BP1

Program and Sector

Program and Sector

(HPM) and BP0 bits cannot be Erase

Erase instructions

changed

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

The protection features of the device are summa-

rized in Table 6.

When the Status Register Write Disable (SRWD)

bit of the Status Register is 0 (its initial delivery

state), it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has

previously been set by a Write Enable (WREN) in-

struction, regardless of the whether Write Protect

(W) is driven High or Low.

When the Status Register Write Disable (SRWD)

bit of the Status Register is set to 1, two cases

need to be considered, depending on the state of

Write Protect (W):

– If Write Protect (W) is driven High, it is possible

to write to the Status Register provided that the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

– If Write Protect (W) is driven Low, it is not pos-

sible to write to the Status Register even if the

Write Enable Latch (WEL) bit has previously

been set by a Write Enable (WREN) instruction.

(Attempts to write to the Status Register are re-

jected, and are not accepted for execution). As

a consequence, all the data bytes in the memo-

ry area that are software protected (SPM) by the

Block Protect (BP1, BP0) bits of the Status Reg-

ister, are also hardware protected against data

modification.

Regardless of the order of the two events, the

Hardware Protected Mode (HPM) can be entered:

– by setting the Status Register Write Disable

(SRWD) bit after driving Write Protect (W) Low

– or by driving Write Protect (W) Low after setting

the Status Register Write Disable (SRWD) bit.

The only way to exit the Hardware Protected Mode

(HPM) once entered is to pull Write Protect (W)

High.

If Write Protect (W) is permanently tied High, the

Hardware Protected Mode (HPM) can never be

activated, and only the Software Protected Mode

(SPM), using the Block Protect (BP1, BP0) bits of

the Status Register, can be used.

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