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IS23SC4428 Просмотр технического описания (PDF) - Integrated Silicon Solution

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IS23SC4428 Datasheet PDF : 12 Pages
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IS23SC4418
IS23SC4428
ISSI ®
IS23SC4428 SECURITY FEATURES
Overview
Without entering Programmable Security Code (PSC), only
memory read access is possible. However, the content of the
PSC addresses (1022 and 1023) cannot be read out. If
reading PSC is attempted, 00H will be output. The PSC
verification procedure must be performed in the following
sequence:
1. Write one to not-written Error Counter bit, address 1021
2. Enter first PSC byte, address 1022
3. Enter second PSC byte, address 1023
4. After successful PSC verification, the Error Counter
should be erased to reactivate the 8 PSC entry attempts.
If the PSC entry is incorrect, go back to step 1. If all the
Error Counter bits have been written, any further PSC
entry will be blocked and the memory can never be
changed again.
Writing Error Counter
The number of erased bits (logic 1) in Error Counter determines
the number of possible attempts (maximum of eight). Before
PSC entry, only writing of error counter is possible. After PSC
is successfully verified, the counter can now be erased.
Before disconnecting the supply voltage Vcc, the counter
should be erased in order to reactivate the eight attempts.
(See Figure 10.)
Entry of PSC
The least significant PSC byte beginning with the least
significant bit must be entered first and then the most significant
(see Table 1). If both PSC byte 1's and byte 2's comparisons
prove correct, the memory erase/write access will be enabled
and PSC may be changed as wished, except the
corresponding protect bits are 0 (enabled). (See Figure 11.)
Condition when supplied
IS23SC4428 is supplied by the manufacturer with a 2-byte
PSC (transport security code) which is determined in
cooperation with the customer.
Command
Entry
Writing Error Counter
RST
0
CLK
23 0 1 2
E/W
(internal
signal)
I/O
S0 S1 D6 D7
Write
Figure 10. Writing Error Counter
99
102
Integrated Silicon Solution, Inc. 1-800-379-4774
9
REV. A
11/01/01

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