HM-6508/883 Просмотр технического описания (PDF) - Intersil
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HM-6508/883 Datasheet PDF : 9 Pages
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HM-6508/883
TRUTH TABLE
INPUTS
OUTPUTS
TIME REFERENCE
E
W
A
D
Q
FUNCTION
-1
H
X
X
X
Z
Memory Disabled
0
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
X
Output Enabled
2
L
H
X
X
V
Output Valid
3
H
X
X
V
Read Accomplished
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
In the HM-6508/883 Read Cycle, the address information is
latched into the on-chip registers on the falling edge of E
(T = 0). Minimum address setup and hold time requirements
must be met. After the required hold time, the addresses
may change state without affecting device operation. During
time (T = 1) the data output becomes enabled; however, the
data is not valid until during time (T = 2).
W must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the chip and force the output buffer to a high impedance
state. After the required E high time (TEHEL) the RAM is
ready for the next memory cycle (T = 4).
Timing Wavforms (continued)
A
E
W
D
O
TIME
REFERENCE
(8) TAVEL
(7)
TEHEL
HIGH 2
TELAX
(9)
VALID
TELEH
(6)
TELEL
(8) TAVEL
TEHEL
TWLEH
(14)
TWLWH
TELWH
(12)
(13)
VALID DATA INPUT
(10)
TDVWH
TWHDX (11)
NEXT
(15)
(7)
-1
0
1
23
4
5
FIGURE 2. WRITE CYCLE
6-74
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