DSP56001 Просмотр технического описания (PDF) - Motorola => Freescale
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DSP56001 Datasheet PDF : 64 Pages
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DSP56001 Electrical Characteristics
AC Electrical Characteristics - Host I/O Timing (Continued)
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see Host Figures 1 through 6)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tHSDL = Host Synchronization Delay Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications
Num
Characteristics
20.5 MHz
Min
Max
46 DMA HACK Deassertion to HREQ
Assertion
(see Note 3)
for DMA RXL Read tHSDL+cyc
—
+tch+5
for DMA TXL Write tHSDL+cyc+5 —
for All Other Cases
5
—
47 Delay from HEN Deassertion to HREQ tHSDL+cyc
—
Assertion for RXL Read (see Note 3) +tch+5
48 Delay from HEN Deassertion to HREQ tHSDL+cyc+5 —
Assertion for TXL Write (see Note 3)
49 Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
5
75
(see Note 3)
27 MHz
Min
Max
tHSDL+cyc
—
+tch+4
tHSDL+cyc+4 —
4
—
tHSDL+cyc
—
+tch+4
tHSDL+cyc+4 —
4
70
33 MHz
Min
Max
tHSDL+cyc
—
+tch+4
tHSDL+cyc+4 —
4
—
tHSDL+cyc
—
+tch+4
tHSDL+cyc+4 —
4
65
Unit
ns
ns
ns
ns
ns
ns
Notes:
1. “Host synchronization delay (tHSDL)” is the time period required for the
DSP56001 to sample any external asynchronous input signal, determine
whether it is high or low, and synchronize it to the DSP56001 internal clock.
2. See HOST PORT USAGE CONSIDERATIONS.
3. HREQ is pulled up by a 1kΩ resistor.
4. This timing must be adhered to only if two consecutive reads from one of these registers are executed.
5. It is recommended that timing #32 be 2cyc+tch+10 minimum for 20.5 MHz, 2cyc+tch+7 minimum for 27 MHz,
and 2cyc+tch+6 minimum for 33 MHz if two consecutive writes to TXL are executed without polling TXDE or
HREQ.
EXTERNAL
INTERNAL
30
30
Host Figure 1. Host Synchronization Delay
DSP56001
MOTOROLA
19
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