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DS1990A-F3

Serial Number iButton

Maxim Integrated 

Serial Number iButton

1-Wire Signaling

The DS1990A requires strict protocols to ensure data

integrity. The protocol consists of four types of signaling

on one line: reset sequence with reset pulse and pres-

ence pulse, write-zero, write-one, and read-data.

Except for the presence pulse, the bus master initiates

all these signals.

To get from idle to active, the voltage on the 1-Wire line

needs to fall from VPUP to below VILMAX. To get from

active to idle, the voltage needs to rise from VILMAX to

above VIHMIN. The time it takes for the voltage to make

this rise, referenced as ε in Figure 6, depends on the

value of the pullup resistor (RPUP) and capacitance of

the 1-Wire network attached.

The initialization sequence required to begin any com-

munication with the DS1990A is shown in Figure 6. A

reset pulse followed by a presence pulse indicates that

the DS1990A is ready to receive a ROM function com-

mand. If the bus master uses slew-rate control on the

falling edge, it must pull down the line for tRSTL + tF to

compensate for the edge.

After the bus master has released the line, it goes into

receive mode (Rx). Now the 1-Wire bus is pulled to

VPUP through the pullup resistor or, in the case of a

DS2480B driver, by active circuitry. When the VIHMIN is

crossed, the DS1990A waits for tPDH and then transmits

a presence pulse by pulling the line low for tPDL. To

detect a presence pulse, the master must test the logi-

cal state of the 1-Wire line at tMSP.

Read/Write Time Slots

Data communication with the DS1990A takes place in

time slots that carry a single bit each. Write time slots

transport data from bus master to slave. Read time

slots transfer data from slave to master. The definitions

of the write and read time slots are illustrated in

Figure 7.

All communication begins with the master pulling the

data line low. As the voltage on the 1-Wire line falls

below VILMAX, the DS1990A starts its internal timing

generator that determines when the data line is sam-

pled during a write time slot and how long data is valid

during a read time slot.

Master-to-Slave

For a write-one time slot, the voltage on the data line

must have risen above VIHMIN after the write-one low

time tW1LMAX is expired. For a write-zero time slot, the

voltage on the data line must stay below VILMAX until

the write-zero low time tW0LMIN is expired. For most reli-

able communication, the voltage on the data line

should not exceed VILMAX during the entire tW0L win-

dow. After the voltage has risen above VIHMIN, the

DS1990A needs a recovery time tREC before it is ready

for the next time slot.

VPUP

VIHMIN

VILMAX

0V

MASTER Tx "RESET PULSE"

tRSTL

tF

RESISTOR

MASTER Rx "PRESENCE PULSE"

ε

tMSP

tPDH

MASTER

tPDL

tRSTH

tREC

DS1990A

Figure 6. Initialization Procedure: Reset and Presence Pulses

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