CY7C68001(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C68001
(Rev.:2004)

High-Speed USB Interface Device

Cypress Semiconductor 

FO R

FO R

CY7C68001

13.0 General PCB Layout Guidelines[15]

The following recommendations should be followed to ensure reliable high-performance operation.

• At least a four-layer impedance controlled boards are re-

quired to maintain signal quality.

• Specify impedance targets (ask your board vendor what

they can achieve).

• To control impedance, maintain trace widths and trace spac-

ing.

• Minimize stubs to minimize reflected signals.

• Connections between the USB connector shell and signal

ground must be done near the USB connector.

• Bypass/flyback caps on VBus, near connector, are recom-

mended.

thermal bond to the circuit board. A Copper (Cu) fill is to be

designed into the PCB as a thermal pad under the package.

Heat is transferred from the SX2 through the device’s metal

paddle on the bottom side of the package. Heat from here, is

conducted to the PCB at the thermal pad. It is then conducted

from the thermal pad to the PCB inner ground plane by a 5 x

5 array of via. A via is a plated through hole in the PCB with a

finished diameter of 13 mil. The QFN’s metal die paddle must

be soldered to the PCB’s thermal pad. Solder mask is placed

on the board top side over each via to resist solder flow into

the via. The mask on the top side also minimizes outgassing

during the solder reflow process.

• DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20–30

mm.

• Maintain a solid ground plane under the DPLUS and DMI-

NUS traces. Do not allow the plane to be split under these

traces.

• It is preferred to have no vias placed on the DPLUS or DMI-

NUS trace routing.

• Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

14.0 Quad Flat Package No Leads (QFN)

Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good

For further information on this package design please refer to

the application note “Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology.” This application note

can be downloaded from AMKOR’s web site from the following

URL

http://www.amkor.com/products/notes_papers/MLF_AppNote

_0902.pdf. The application note provides detailed information

on board mounting guidelines, soldering flow, rework process,

etc.

Figure 14-1 below display a cross-sectional area underneath

the package. The cross section is of only one via. The solder

paste template needs to be designed to allow at least 50%

solder coverage. The thickness of the solder paste template

should be 5 mil. It is recommended that “No Clean” type 3

solder paste is used for mounting the part. Nitrogen purge is

recommended during reflow.

Cu Fill

0.017” dia

Solder Mask

Cu Fill

PCB Material

0.013” dia

PCB Material

Via hole for thermally connecting the

QFN to the circuit board ground plane.

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and the Ground Plane.

Figure 14-1. Cross section of the Area Underneath the QFN Package

Figure 14-2a is a plot of the solder mask pattern and Figure 14-2b displays an X-Ray image of the assembly (darker areas indicate

solder.

Figure 14-2. (a) Plot of the Solder Mask (White Area)

Figure 14-2(b) X-ray Image of the Assembly

Note:

15. Source for recommendations: High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.

Document #: 38-08013 Rev. *E

Page 38 of 42

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