C8051F020 Просмотр технического описания (PDF) - Silicon Laboratories

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C8051F020

8K ISP FLASH MCU Family

Silicon Laboratories 

C8051F020/1/2/3

Figure 23.4. PCA Capture Mode Diagram ............................................................................253

Figure 23.5. PCA Software Timer Mode Diagram................................................................254

Figure 23.6. PCA High Speed Output Mode Diagram ..........................................................255

Figure 23.7. PCA Frequency Output Mode ...........................................................................256

Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................................257

Figure 23.9. PCA 16-Bit PWM Mode ...................................................................................258

Figure 23.10. PCA0CN: PCA Control Register ....................................................................259

Figure 23.11. PCA0MD: PCA0 Mode Register ....................................................................260

Figure 23.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers .................................261

Figure 23.13. PCA0L: PCA0 Counter/Timer Low Byte .......................................................262

Figure 23.14. PCA0H: PCA0 Counter/Timer High Byte ......................................................262

Figure 23.15. PCA0CPLn: PCA0 Capture Module Low Byte ..............................................263

Figure 23.16. PCA0CPHn: PCA0 Capture Module High Byte .............................................263

24. JTAG (IEEE 1149.1)............................................................................................................265

Figure 24.1. IR: JTAG Instruction Register ..........................................................................265

Table 24.1. Boundary Data Register Bit Definitions............................................................266

Figure 24.2. DEVICEID: JTAG Device ID Register ............................................................267

Figure 24.3. FLASHCON: JTAG Flash Control Register.....................................................269

Figure 24.4. FLASHADR: JTAG Flash Address Register ....................................................270

Figure 24.5. FLASHDAT: JTAG Flash Data Register..........................................................270

Rev. 1.4

15

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