ATXMEGA32A4(2008) Просмотр технического описания (PDF) - Atmel Corporation
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ATXMEGA32A4 Datasheet PDF : 74 Pages
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XMEGA A4
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 10. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address
ATxmega64A4
Byte Address
ATxmega32A4
Byte Address
ATxmega16A4
0
I/O Registers
FFF
(4KB)
0
I/O Registers
FFF
(4KB)
0
I/O Registers
FFF
(4KB)
1000
17FF
EEPROM
(2K)
1000
17FF
EEPROM
(2K)
1000
17FF
EEPROM
(1K)
RESERVED
RESERVED
RESERVED
2000
2FFF
Internal SRAM
(4K)
2000
2FFF
Internal SRAM
(4K)
2000
27FF
Internal SRAM
(2K)
3000
FFFFFF
External Memory
(0 to 16 MB)
3000
FFFFFF
External Memory
(0 to 16 MB)
2800
FFFFFF
External Memory
(0 to 16 MB)
7.4.1
Byte Address
0
FFF
1000
17FF
2000
3FFF
4000
FFFFFF
ATxmega128A4
I/O Registers
(4KB)
EEPROM
(2K)
RESERVED
Internal SRAM
(8K)
External Memory
(0 to 16 MB)
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A4 is shown in the ”Periph-
eral Module Address Map” on page 51.
10
8069D–AVR–08/08
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