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74VHCT132AM

QUAD 2-INPUT SCHMITT NAND GATE

STMicroelectronics 

74VHCT132A

QUAD 2-INPUT SCHMITT NAND GATE

s HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

s TYPICAL HYSTERESIS : 0.7V at VCC = 4.5V

s POWER DOWN PROTECTION ON INPUTS

& OUTPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 132

s IMPROVED LATCH-UP IMMUNITY

s LOW NOISE: VOLP = 0.8V (MAX.)

DESCRIPTION

The 74VHCT132A is an advanced high-speed

CMOS QUAD 2-INPUT SCHMITT NAND GATE

fabricated with sub-micron silicon gate and

double-layer metal wiring C2MOS technology.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V since all

inputs are equipped with TTL threshold.

SOP

TSSO P

ORDER CODES

PACKAGE

TUBE

T &R

SOP

TSSOP

74VHCT132AM 74VHCT132AMTR

74VHCT132ATTR

Pin configuration and function are the same as

those of the 74VHCT00A but the 74VHCT132A

has hysteresis.

This, together with its schmitt trigger function,

allows it to be used on line receivers with slow

rise/fall input signals.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2001

1/8

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