VV0670P001 Просмотр технического описания (PDF) - Vision

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VV0670P001

Colour Processor Interface ASIC

Vision 

Colour Processor Interface ASIC

Effect of LOPOW on CPiA-based module power consuption WITH EXTERNAL CONTROL OF VDDA using external FET.

NORM is shown for reference only and is not required for power control using external FET.

LOPOW NORM

Mode

Description

VDDA

Approx

Module

Current

CPiA, camera module and DRAM components are in lowest power

1

1

Suspend

mode. VDDA is withdrawn as external FET is off, all fast clocks are

0V

<500uA

disabled and CPiA logic is in held reset

CPiA is in low power mode. Fast clocks enabled and CPiA can process

0

1

Low Power

commands from host PC. Camera, video processing and DRAM

5V

<50mA

controller modules are held in reset

0

0

High Power

All CPiA modules, camera and DRAM components are active and video

data is being transferred to host PC.

5V

<250mA

If VDDA is not controlled using VDDA (VDD=VDDA=VDDU) in parallel port modes of operation, approx module power

consumption will be <250mA at all times. In such cases, LOPOW and NORM can be considered redundant.

CPiA’s power management block requires two externally derived inputs: RESET provides a global reset to all

CPiA logic and CLK400H provides a low frequency clock to CPiA’s internal power control state machines and

should be constrained in accordance with the timing diagrams presented below. The Events are also

described in the table below. After event RR, the process returns to CSU.

Event POR CSU

Trl

RESET

Trp

Tp

CLK400H

LOWPO

Tllp

VDDA

Trvda

CKI14

Tck1su

CKI48

Tck2su

NORM

SCLK

LPM

RHP

Trhp

HPI

Tnhpm

Tnsclk

HPM

SR SUSP

RR CSU

Tsrs

Trrc

Timing Diagram Highlighting Power Management Events

V:\apps\cpia\docs\cpia datasheet\cpia_datasheet4.fm

02/07/98

11

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