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SSD1854U

LCD Segment / Common Driver with Controller CMOS

Solomon Systech  

7.14 Read Status Byte

An 8 bits status byte will be placed to the data bus if a read operation is performed if D/ C is low. The

status byte is defined as follow.

Table 6 - Read Status Byte

D7 D6 D5 D4 D3 D2 D1 D0 Command

BUSY ON RES 0 1 0 1 1 Read Status

Comment

BUSY=0: Chip is idle

BUSY=1: Chip is executing instruction

ON=0: Display is OFF

ON=1: Display is ON

RES=0: Chip is idle

RES=1: Chip is executing reset

7.15 Data Read / Write

To read data from the GDDRAM, input High to R/W( WR ) pin and D/ C pin for 6800-series parallel

mode. Low to E( RD ) pin and High to D/ C pin for 8080-series parallel mode. A complete data read

cycle must issue two clocks to read both First Byte and Second Byte from GDDRAM. No data read is

provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one

automatically after each complete data read cycle. Also, a dummy read is required before the first data

is read. See Figure 3 in Functional Description.

To write data to the GDDRAM, input Low to R/W( WR ) pin and High to D/ C pin for 6800-series parallel

mode. High to E( RD ) pin and Low to D/ C pin for 8080-series parallel mode. A complete data write

cycle must issue two clocks to write both First Byte and Second Byte to GDDRAM. For serial interface,

it will always be in write mode. GDDRAM column address pointer will be increased by one

automatically after each complete data write cycle. The column address will be reset to 0 in next data

read/write operation is executed when it is 127.

Table 7 - Address Increment Table (Automatic)

D/ C

0

0

1

1

R/W ( WR )

0

1

0

1

Comment

Write Command

Read Status

Write Data

Read Data

Address Increment

No

No

Yes

Yes

Address Increment is done automatically after two data read/write. The column address pointer of

GDDRAM is also affected. It will be reset to 0 after 127. It should be noted that the page address will

NOT be changed when this warp round happens.

Table 8 - Commands Required for R/W ( WR ) Actions on RAM

R/W ( WR ) Actions on RAMs

Commands Required

Read/write Data from/to GDDRAM Set GDDRAM Page Address

Set GDDRAM Column Address

Read/Write Data

* No need to resend the command again if it is set previously.

(1011XXXX)*

(X7X6X5X4X3X2X1X0)*

(00010X2X1X0)*

(0000X3X2X1X0)*

(X7X6X5X4X3X2X1X0)

The read / write action to the Display Data RAM does not depend on the display mode. This means the

user can change the RAM content whether the target RAM content is being displayed or not.

25

SSD1854

Series

Rev 1.0

08/2002

SOLOMON

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