Symbol
FSCL
TCLKL
TCLKH
TDSW
TDHW
TR
TF
CBUS
TDH, START
TDS, STOP
Parameter
I2C-bus Clock frequency, SCL
I2C-bus Clock Low period, SCL
I2C-bus Clock high period, SCL
I2C-bus Data Setup time, SDA
I2C-bus Data Hold time, SDA
Rise time between SDA & SCL
Fall time between SDA & SCL
Capacitive loadings at each I2C-bus channel
I2C-bus Hold time, START condition
I2C-bus Setup time, STOP condition
Min
Typ Max Unit
0
- 400 kHz
1.3
--
s
0.6
--
s
100
--
s
0.3
- 0.9 s
20+0.1CBUS - 300 ns
20+0.1CBUS - 300 ns
-
- 400 pF
0.6
--
s
0.6
--
s
Table 10 - I2C-bus timing Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD =
1.8 to 3.3V, TA =-20 to +70°C)
T DH, START
T DHW
T DSW
T Cycle
TR
T CLKH
TF
T CLKL
T DS, STOP
Figure 17 - I2C data bus Interface driving waveform
39
SSD0858
Rev 1.0
11/2002
SOLOMON