GL800USB Просмотр технического описания (PDF) - Genesys Logic

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GL800USB

3.3 V, USB 2.0 UTMI compliant transceiver

Genesys Logic 

GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER

4.2 Functional Overview

4.2.1 HS XCVR

HS XCVR contains the low-level analog circuitry required to physically interface

USB 2.0 signaling to the USB DP/DM signal lines.

4.2.2 FS XCVR

FS XCVR includes the logic necessary to send and receive the FS data on USB.

4.2.3 Clock Multiplier

Clock Multiplier generates the internal clocks for the GL800USB USB 2.0

Transceiver and the CLKOUT signal. All data transfer signals are synchronized

with the CLKOUT signal.

In HS mode there is one clock cycle per byte time. The frequency of clock does not

change when the UTMI is switched between HS to FS modes. In FS mode there

are 5 clock cycles per FS bit time, typically 40 clock cycles per FS byte time. If a

received byte contains a stuffed bit then the byte boundary can be stretched to 45

clock cycles, and two stuffed bits would result in a 50 clock delay between bytes.

4.2.4 HS DLL (High Speed Delay Line PLL)

DLL extracts clock and data from the data received over the USB 2.0 interface for

reception by the Receive Deserializer. The data output from the DLL is

synchronous with the local clock.

4.2.5 Elasticity Buffer

Elasticity Buffer is used to compensate for difference between transmitting and

receiving clocks. The USB specification defines a maximum clock error of +/- 500

ppm. When the error is calculated over the maximum packet size up to +/- 12 bits

of drift can occur. The elasticity buffer is filled to a threshold prior to enabling the

remainder of the down stream receive logic.

Overview and underflow conditions detected in the elasticity buffer can be reported

with the RXERR signal.

4.2.6 Mux

The MUX block allows the data from the HS or FS receivers to be routed to the

shared receive logic. The state of the Mux is determined by the FSPEED input.

4.2.7 NRZI Decoder

The NRZI Decoder is compliant to standard USB 1.X specification, and it can

operate at FS and HS data rates.

©2000-2001 Genesys Logic Inc.—All rights reserved.

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