GL800USB Просмотр технического описания (PDF) - Genesys Logic

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производитель

GL800USB

3.3 V, USB 2.0 UTMI compliant transceiver

Genesys Logic 

GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER

!SYNC

HRST#

Reset

!RXACTV

!HRST#

RX Wait

Terminate

!RXACTV

!RXVLD

Strip EOP

SYNC Detected

Trip SYNC

Data

Rx Data

!RXACTV

EOP

!RXVLD

Detected

Abort 1

Idle

state

RXACTV

Data

RXVLD

!RXACTV

!RXVLD

SYNC

!Data

Data

RX Data Wait

Receive

Error

Error

RXERR

!RXERR

Abort 2

!RXVLD

!RXERR

!RXVLD

!Data

!Idle

state

RXACTV and RXVLD are sampled on the rising edge of CLKOUT.

In the RX Wait state the receiver is always looking for SYNC.

The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state).

The Macrocell negates RXACTV when an EOP is detected (Strip EOP state).

When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is

full.

RXVLD will be negated if the RX Holding Register was not loaded during the

previous byte time. This will occur if 8 stuffed bits have been accumulated.

The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted

(RX Data state).

In FS mode, if a bit stuff error is detected then the Receive State Machine will negate

RXACTV and RXVLD, and return to the RXWait state.

6.2.2 Receive Timing for Data Packet (with CRC-16)

©2000-2001 Genesys Logic Inc.—All rights reserved.

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