GL800USB Просмотр технического описания (PDF) - Genesys Logic

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производитель

GL800USB

3.3 V, USB 2.0 UTMI compliant transceiver

Genesys Logic 

GL800USB - USB2.0 UTMI COMPLIANT TRANSCEIVER

Pin # Name

26 TXRDY

27 D 0

28 D 1

29 D 2

30 D 3

31 DVCC0

32 DGND0

33 D 4

34 D 5

35 D 6

36 D 7

37 D 8

38 D 9

39 D 10

40 D 11

41 DVCC1

42 DGND1

43 D 12

44 D 13

45 D 14

46 D 15

Pull

I/O

Up/Down

Description

Transmit data ready, active high. If TXVLD is

asserted, the SIE must always have data

available for clocking in to the TX Register on the

rising edge of CLKOUT. If TXVLD is true and

TXRDY is asserted at the rising edge of CLKOUT,

the GL800USB will load the data on the Data bus

O

into the TX Register on the next rising edge of

CLKOUT, at that time, SIE should immediately

present the data for next transfer on the Data bus.

If TXVLD is asserted and TXRDY is negated, the

SIE must hold the previously asserted data on the

Data bus. From the time TXVLD is negated,

TXRDY is a don’t care for the SIE.

B

Data bus 0

B

Data bus 1

B

Data bus 2

B

Data bus 3

P

Positive digital supply (3.3V)

P

Digital ground (0V)

B

Data bus 4

B

Data bus 5

B

Data bus 6

B

Data bus 7

B

Data bus 8

B

Data bus 9

B

Data bus 10

B

Data bus 11

P

Positive digital supply (3.3V)

P

Digital ground (0V)

B

Data bus 12

B

Data bus 13

B

Data bus 14

B

Data bus 15

©2000-2001 Genesys Logic Inc.—All rights reserved.

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