GM5110 Просмотр технического описания (PDF) - Genesis Microchip

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GM5110

XGA/SXGA LCD Controller

Genesis Microchip 

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gm5110/20 Preliminary Data Sheet

Vdd

14 to 24 MHz

Vdd

Oscillator

GND

Vdd

152

TCLK

151

XTAL

10 K

10

ROM_ADDR13

gm5110/20

Internal

Oscillator

Disable

OSC_OUT

TCLK Distribution

Reset State Logic

External Oscillator Enable

Internal Pull Down

Resistor

~ 60 K

Figure 7.

Using an External Single-ended Clock Oscillator

Frequency

Jitter Tolerance

Rise Time (10% to 90%)

Maximum Duty Cycle

14 to 24 MHz

250 ps

5 ns

40-60

Table 13. TCLK Specification

4.1.3 Clock Synthesis

The gm5110/20 synthesizes all additional clocks internally as illustrated in Figure 8 below.

The synthesized clocks are as follows:

1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is

derived from the TCLK/XTAL pad input.

2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the

reference.

3. DVI Input Clock (DVI_CLK) synthesized by DVI receiver PLL using RC+/RC- pair as

the reference.

4. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input

HSYNC as the reference. The SDDS internal digital logic is driven by RCLK.

June 2002

14

C5110-DAT-01C

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