GM2115 Просмотр технического описания (PDF) - Genesis Microchip
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GM2115 Datasheet PDF : 54 Pages
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*** Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
3. GM2115/25 PIN LIST
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground
Pin Name
AVDD_RED
RED+
RED-
AGND_RED
AVDD_GREEN
GREEN+
GREEN-
AGND_GREEN
AVDD_BLUE
BLUE+
BLUE-
AGND_BLUE
AVDD_ADC
ADC_TEST
AGND_ADC
SGND_ADC
GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
HSYNC
VSYNC
Table 1. Analog Input Port
No. I/O Description
172 AP
171 AI
170 AI
169 AG
168 AP
167 AI
166 AI
165 AG
164 AP
163 AI
162 AI
161 AG
160 AP
159 AO
158 AG
157 AG
156 G
155 P
154 G
153 P
137 I
136 I
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
Analog test output for ADC Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.
Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the analog system ground plane.
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane.
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
Pin Name
AVDD_RPLL
AVSS_RPLL
TCLK
XTAL
VDD_RPLL
VSS_RPLL
Table 2. RCLK PLL Pins
No I/O Description
150 AP
149 AG
152 AI
151 AO
148 P
147 G
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-
ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 13.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
June 2002
8
C2115-DAT-01B
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