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Chapter 1 Overview

2.7 Loop Instruction Register

LIR: Loop Instruction Register (32 bits x 1)

This 32-bit register, used only by the SETLB (Set Loop Beginning) and Lcc (Loop) instructions, holds the

first four instruction bytes of the loop for use in speeding up iterations. The SETLB instruction loads it prior

to the loop, and the Lcc instruction at the end of the loop then executes the copy while the pipeline fetches

more instruction bytes starting from the fifth.

For further details, see the SETLB description in Chapter 2.

2.8 Loop Address Register

LAR: Loop Address Register (32 bit x 1)

This 32-bit register, used only by the SETLB (Set Loop Beginning) and Lcc (Loop) instructions, holds the

address of the fifth instruction byte of the loop.

6

Register Set

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