CDB5342 Просмотр технического описания (PDF) - Cirrus Logic
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CDB5342 Datasheet PDF : 22 Pages
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CS5342
4.2.3 Master Clock
The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also
an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 3 shows a list-
ing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and
the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with
a fast MCLK (768x, 384x, 192x for Single, Double, and Quad Speed Modes respectively).
MCLK/LRCK Ratio
Single Speed Mode
384x, 768x
Double Speed Mode
192x, 384x
Quad Speed Mode
96x*, 192x
* Quad Speed, 96x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)
32
44.1
48
64
88.2
96
192
MCLK (MHz)
12.288
16.9344
33.8688
18.432
36.864
12.288
16.9344
33.8688
18.432
36.864
36.864
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3 Serial Audio Interface
The CS5342 supports both I2S and Left Justified serial audio formats. Upon start-up, the CS5342 will detect the logic
level on SDOUT (pin 4). A 10 kΩ pull-up resistor to VL is needed to select I2S format, and a 10 kΩ pull-down resistor
to GND is needed to select Left Justified format. Please see Figures 13 through 16 on page 12, for more information
on the required timing for the two serial audio interface formats.
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22 9 8 7 6 5 4 3 2 1 0
23 22 9 8 7 6 5 4 3 2 1 0
Figure 19. Left-Justified Serial Audio Interface
23 22
LRCK
Left Channel
Right Channel
SCLK
SDATA
23 22
9876543210
23 22 9 8 7 6 5 4 3 2 1 0
Figure 20. I2S Serial Audio Interface
23 22
DS608PP2
17
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