LTC2607 Просмотр технического описания (PDF) - Linear Technology
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LTC2607 Datasheet PDF : 20 Pages
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LTC2607/LTC2617/LTC2627
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,
VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS
Settling Time (Note 7)
±0.024% (±1LSB at 12 Bits)
7
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
µs
9
9
µs
10
µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
2.7
2.7
2.7
µs
(Note 8)
±0.006% (±1LSB at 14 Bits)
4.8
4.8
µs
±0.0015% (±1LSB at 16 Bits)
5.2
µs
Voltage Output Slew Rate
0.8
0.8
0.8
V/µs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
12
12
12
nV • s
Multiplying Bandwidth
180
180
180
kHz
en
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
120
120
nV/√Hz
100
100
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
µVP-P
WU
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
tHD(STA) Hold Time (Repeated) Start Condition
tLOW
Low Period of the SCL Clock Pin
tHIGH
High Period of the SCL Clock Pin
tSU(STA) Set-Up Time for a Repeated Start Condition
tHD(DAT) Data Hold Time
tSU(DAT) Data Set-Up Time
tr
Rise Time of Both SDA and SCL Signals
tf
Fall Time of Both SDA and SCL Signals
tSU(STO) Set-Up Time for Stop Condition
tBUF
Bus Free Time Between a Stop and Start Condition
(Note 9)
(Note 9)
●
0
●
0.6
●
1.3
●
0.6
●
0.6
●
0
●
100
● 20 + 0.1CB
● 20 + 0.1CB
●
0.6
●
1.3
400
kHz
µs
µs
µs
µs
0.9
µs
ns
300
ns
300
ns
µs
µs
t1
Falling Edge of 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
●
400
ns
t2
LDAC Low Pulse Width
●
20
ns
Note 1: Absolute maximum ratings are those values beyond which the life of
a device may be impaired.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256
and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL and LDAC at 0V or VCC, CA0, CA1 and CA2 Floating.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the
measured DAC at midscale, unless otherwise noted.
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Inferred from measurement at code kL (Note 2) and at full scale.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2607/LTC2607-1,
LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.
4
26071727f
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