PIC12F635 Просмотр технического описания (PDF) - Unspecified

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PIC12F635

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Unspecified 

PIC12F635/PIC16F636/639

TABLE 2-2: PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Addr Name Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on Value on

POR/BOD/ all other

WUR

Resets(1)

Bank 0

00h INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx xxxx xxxx

01h TMR0 Timer0 Module Register

xxxx xxxx uuuu uuuu

02h PCL

Program Counter’s (PC) Least Significant Byte

0000 0000 0000 0000

03h STATUS IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

04h FSR

Indirect Data Memory Address Pointer

xxxx xxxx uuuu uuuu

05h GPIO

—

—

GP5

GP4

GP3

GP2

GP1

GP0 --xx xx00 --uu uu00

06h

— Unimplemented

—

—

07h

— Unimplemented

—

—

08h

— Unimplemented

—

—

09h

— Unimplemented

—

—

0Ah PCLATH —

0Bh INTCON GIE

—

PEIE

— Write Buffer for upper 5 bits of Program Counter

---0 0000 ---0 0000

T0IE

INTE

RAIE

T0IF

INTF

RAIF(2) 0000 0000 0000 0000

0Ch PIR1

EEIF LVDIF CRIF

—

C1IF OSFIF

—

TMR1IF 000- 00-0 000- 00-0

0Dh

— Unimplemented

—

—

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1

xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1

xxxx xxxx uuuu uuuu

10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

11h

— Unimplemented

—

—

12h

— Unimplemented

—

—

13h

— Unimplemented

—

—

14h

— Unimplemented

—

—

15h

— Unimplemented

—

—

16h

— Unimplemented

—

—

17h

— Unimplemented

—

—

18h WDTCON —

—

— WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

19h CMCON0 — C1OUT —

C1INV

CIS

CM2

CM1

CM0 -0-0 0000 -0-0 0000

1Ah CMCON1 —

—

—

—

—

—

T1GSS CMSYNC ---- --10 ---- --10

1Bh

— Unimplemented

—

—

1Ch

— Unimplemented

—

—

1Dh

— Unimplemented

—

—

1Eh

— Unimplemented

—

—

1Fh

— Unimplemented

—

—

Legend:

Note 1:

2:

— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

© 2005 Microchip Technology Inc.

Preliminary

DS41232B-page 15

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