NT68520 Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

производитель

NT68520

XGA, SXGA Flat Panel Monitor Controller

Unspecified 

NT68520X,E

signal ranging from 0.5V to 1.0V（p-p）, the ADC’s full-scale input level is 1V（p-p）.

Three independent registers are used to adjust the signal level (gain), the relation

between the gain and register value is as follows:

Gain = 0.8 + 1.2/ 255 * Gain <7:0>

Gain<7:0>

Input Signal(0.5V~1.2V)

Gain

Output Signal(1.0V)

Phase-locked loop

The internal PLL locks to the HSYNC input (frequency range 15~100 KHz) and derives a

sampling clock (CKOUT) to internal ADC. The bandwidth of PLL is from 16 MHz to 135

MHz.

Low Pass Filter

COAST

VCON

Cp

Cz

Cz

CKEXT

INV

HSYNC

Polarity Select (1 bit)

PLL diagram

2003/4/15

Phase

Frequency

Detector

12 to 135Mhz

VCO

32 Step

Phase

Adjust

5 bit

11 bit

Divider N

1 to 2048

15

Inverter

1 bit

CKOUT

Ver.1.0

Share Link: