AD9911 Просмотр технического описания (PDF) - Analog Devices
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AD9911 Datasheet PDF : 41 Pages
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AD9911
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC_IN 1
SYNC_OUT 2
MASTER_RESET 3
PWR_DWN_CTL 4
AVDD 5
NC 6
AVDD 7
AVDD 8
AVDD 9
NC 10
AVDD 11
NC 12
AVDD 13
AVDD 14
PIN 1
INDICATOR
AD9911
TOP VIEW
(Not to Scale)
42 P2
41 P1
40 P0
39 AVDD
38 AGND
37 AVDD
36 IOUT
35 IOUT
34 AGND
33 AVDD
32 NC
31 AVDD
30 AVDD
29 AVDD
Data Sheet
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1
SYNC_IN
2
SYNC_OUT
3
MASTER_RESET
4
5, 7, 8, 9, 11, 13, 14,
15, 19, 21, 26, 29,
30, 31, 33, 37, 39
18, 20, 25, 34, 38
45, 55
44, 56
35
36
17
PWR_DWN_CTL
AVDD
AGND
DVDD
DGND
IOUT
IOUT
DAC_RSET
22
REF_CLK
23
REF_CLK
24
CLK_MODE_SEL
27
LOOP_FILTER
NC = NO CONNECT
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
Figure 6. Pin Configuration
I/O Description
I
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_OUT pin of the master
AD9911 device.
O
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_IN pin of the slave
AD9911 device.
I
Active High Reset Pin. Asserting this pin forces the internal registers to the default
state shown in the Register Map section.
I
External Power-Down Control. See the Power Down Functions section for details.
I
Analog Power Supply Pins (1.8 V).
I
Analog Ground Pins.
I
Digital Power Supply Pins (1.8 V).
I
Digital Power Ground Pins.
O
Complementary DAC Output. Terminates into AVDD.
O
True DAC Output. Terminates into AVDD.
I
Establishes the Reference Current for the DAC. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
I
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in
single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 µF capacitor.
I
Reference Clock/Oscillator Input. When the REF_CLK operates in single-ended mode,
Pin 23 is the input. See the Modes of Operation section for the reference clock
configuration.
I
Control Pin for the Oscillator. CAUTION: Do not drive this pin beyond 1.8 V. When high
(1.8 V), the oscillator is enabled to accept a crystal as the REF_CLK source. When low,
the oscillator is bypassed.
I
Connects to the External Zero Compensation Network of the PLL Loop Filter. Typically,
the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.
Rev. A | Page 10 of 41
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