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UPSD3253BV

Flash Programmable System Devices with 8032 Microcontroller Core

STMicroelectronics 

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Figure 9. PSW (Program Status Word) Register

MSB

PSW CY AC FO RS1 RS0 OV

Carry Flag

Auxillary Carry Flag

General Purpose Flag

LSB

P Reset Value 00h

Parity Flag

Bit not assigned

Overflow Flag

Register Bank Select Flags

(to select Bank0-3)

AI06639

Program Memory

The program memory consists of two Flash mem-

ory: 128 KByte (or 256 KByte) Main Flash and 32

KByte of Secondary Flash. The Flash memory can

be mapped to any address space as defined by

the user in the PSDsoft Tool. It can also be

mapped to Data memory space during Flash

memory update or programming.

After reset, the CPU begins execution from loca-

tion 0000h. As shown in Figure 10, each interrupt

is assigned a fixed location in Program Memory.

The interrupt causes the CPU to jump to that loca-

tion, where it commences execution of the service

routine. External Interrupt 0, for example, is as-

signed to location 0003h. If External Interrupt 0 is

going to be used, its service routine must begin at

location 0003h. If the interrupt is not going to be

used, its service location is available as general

purpose Program Memory.

The interrupt service locations are spaced at 8-

byte intervals: 0003h for External Interrupt 0,

000Bh for Timer 0, 0013h for External Interrupt 1,

001Bh for Timer 1 and so forth. If an interrupt ser-

vice routine is short enough (as is often the case

in control applications), it can reside entirely within

that 8-byte interval. Longer service routines can

use a jump instruction to skip over subsequent in-

terrupt locations, if other interrupts are in use.

Data memory

The internal data memory is divided into four phys-

ically separated blocks: 256 bytes of internal RAM,

128 bytes of Special Function Registers (SFRs)

areas, 256 bytes of external RAM (XRAM-DDC)

and 32K bytes (XRAM-PSD) in the PSD Module.

RAM

Four register banks, each 8 registers wide, occupy

locations 0 through 31 in the lower RAM area.

Only one of these banks may be enabled at a time.

The next 16 bytes, locations 32 through 47, con-

tain 128 directly addressable bit locations. The

stack depth is only limited by the available internal

RAM space of 256 bytes.

Figure 10. Interrupt Location of Program

Memory

•

•

•

Interrupt

•

•

Location

Reset

008Bh

•

•

•

•

0013h

000Bh

8 Bytes

0003h

0000h

AI06640

XRAM-DDC

The 256 bytes of XRAM-DDC used to support

DDC interface is also available for system usage

by indirect addressing through the address pointer

DDCADR and data I/O buffer RAMBUF. The ad-

dress pointer (DDCADR) is equipped with the post

increment capability to facilitate the transfer of

data in bulk (for details refer to DDC Interface

part). However, it is also possible to address the

RAM through MOVX command as normally used

in the internal RAM extension of 80C51 deriva-

tives. XRAM-DDC FF00 to FFFF is directly ad-

dressable as external data memory locations

FF00 to FFFF via MOVX-DPTR instruction or via

MOVX-Ri instruction. When XRAM-DDC is dis-

abled, the address space FF00 to FFFF can be as-

signed to other resources.

XRAM-PSD

The 32K bytes of XRAM-PSD resides in the PSD

Module and can be mapped to any address space

through the DPLD (Decoding PLD) as defined by

the user in PSDsoft Development tool. The XRAM-

PSD has a battery backup feature that allow the

data to be retained in the event of a power lost.

The battery is connected to the Port C PC2 pin.

This pin must be configured in PSDSoft to be bat-

tery back-up.

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