Z8018233FSC Просмотр технического описания (PDF) - Zilog

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Z8018233FSC

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

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PRELIMINARY

ASCI CHANNELS CONTROL REGISTERS (Continued)

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Bit

Upon RESET

R/W

CNTLA1

MPE RE

0

0

R/W R/W

TE

0

R/W

Addr 01H

CKA1D MPBR/ MOD2 MOD1 MOD0

EFR

1

x

0

0

0

R/W R/W R/W R/W R/W

MODE Selection

0

0

0 Start + 7-Bit Data + 1 Stop

0

0

1 Start + 7-Bit Data + 2 Stop

0

1

0 Start + 7-Bit Data + Parity + 1 Stop

0

1

1 Start + 7-Bit Data + Parity + 2 Stop

1

0

0 Start + 8-Bit Data + 1 Stop

1

0

1 Start + 8-Bit Data + 2 Stop

1

1

0 Start + 8-Bit Data + Parity + 1 Stop

1

1

1 Start + 8-Bit Data + Parity + 2 Stop

Read - Multiprocessor Bit Receive

Write - Error Flag Reset

CKA1 Disable

Transmit Enable

Receive Enable

Multiprocessor Enable

Figure 10b. ASCI Control Register A (Ch. 1)

3-30

PS009801-0301

DS971820600

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