Z80182 Просмотр технического описания (PDF) - Zilog

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производитель

Z80182

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog 

Zilog

PRELIMINARY

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

Z85230 ESCC™ BLOCK DIAGRAM

For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block

diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to "INTO of the

Z182.

Channel A

Exploded View

Transmit Logic

Transmit FIFO

4 Bytes

Transmit MUX

Data Encoding & CRC

Generation

Receive and Transmit Clock Multipexer

Digital

Phase-Locked

Loop

Baud Rate

Generator

Crystal

Oscillator

Amplifier

TxDA

/TRxCA

/RTxCA

Modem/Control Logic

Receive Logic

Rec. Status* Rec. Data*

FIFO

FIFO

Receive MUX

/CTSA

/DCDA

/SYNCA

/RTSA

/DTRA//REQA

RxDA

SDLC Frame Status FIFO

10 x 19

CRC Checker,

Data Decode &

Sync Character

Detection

* 8 bytes each

Databus

Control

CPU & DMA

Bus Interface

Interrupt

Control

/INT

/INTACK

IEI

IEO

Internal

Control

Logic

Interrupt

Control

Logic

Channel A

Register

Channel B

Register

Figure 5. ESCC Block Diagram

Channel A

Channel B

3-20

PS009801-0301

DS971820600

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