Z8018233ASD Просмотр технического описания (PDF) - Zilog

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Z8018233ASD

ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

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PRELIMINARY

/HRD

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

/HDDIS

13

Figure 113. Driver Enable Timing

Table J. Driver Enable Timing

No.

Sym

Parameter

Z8L182

20 MHz

Min Max

13

tRDD

/HRD to Driver

Enable/Disable

60

Note:

These AC parameter values are preliminary and are subject to change without notice.

/WR (MPU)

RBR

HINTR

(Trigger

Level)

HINTR

(Line

Status

RDR

/HRD LSR

14

14

15

Z80182

33 MHz

Min Max

60

Units

ns

/HRD RBR

15

Figure 114. Interrupt Timing RCVR FIFO

DS971820600

PS009801-0301

3-103

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