HI1260JCQ Просмотр технического описания (PDF) - Intersil
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HI1260JCQ Datasheet PDF : 13 Pages
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HI1260
However, when it is made to RL ≤ 10kΩ the temperature
characteristics may change considerably. In addition,
when it is made to CL ≤ 20pF, the rise and fall of the D/A
output become slow and will not operate at high speed.
• Noise Reduction Measures
As the D/A output voltage is a minute voltage of
approximately 4mV per one step, ingenuity is required in
reducing the noise entering from the outside of the IC as
much as possible. Therefore, use the items given below as
reference.
When mounting onto the printed board, allow as much
space as possible to the ground surface and the VCC
surface on the board and reduce the parasitic inductance
and resistance.
It is desirable that the AGND and DGND be separated in
the pattern on the board. It is similar with AVCC and
DVCC. As shown in the diagram below, for example, it is
recommended that the wiring to the electric supply of
AGND and DGND as also AVCC and DVCC be conducted
separately, and then making AGND and DGND as also
AVCC and DVCC in common right near the power supply
respectively.
Inset in parallel a 47µF tantalum capacitor and a 100pF
ceramic capacitor between the VCC surface on the printed
board and the nearmost ground surface (A of diagram
below). It is also desirable to insert the above between the
VCC surface near the pin of the IC and the ground surface
(B of diagram below). They are bypass capacitors to pre-
vent bad effects from occurring to the characteristics when
the power supply voltage fluctuates due to the clock, etc.
It is recommended to reduce noise which overlaps the D/A
output by inserting a capacitor of over 0.1µF between pin 23
(AGND) and pin 24 (VSET).
CXI260Q-Z
A
PRINTED BOARD
DGND
AVCC
DVCC
AGND
B
POWER SUPPLY
FIGURE 20.
10-13
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