SAA7780 Просмотр технического описания (PDF) - Philips Electronics

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SAA7780

ThunderBird Q3D™ PCI Audio Accelerator

Philips Electronics 

Philips Semiconductors

Product Specification

ThunderBird Q3D PCI Audio

Accelerator

SAA7780

General Purpose Input/Output

There are five general purpose I/O pins that are controlled by the DSP. These pins can be used for power management

of external devices or for test and debug of DSP code. All are full time available under DSP code control. These GPIOs

are not controllable from the PCI bus and are generally not available to users.

PINE DSP Core

The Pine DSP core is a programmable 16-bit integer DSP with separate code and data busses (Harvard architecture).

Main features of the DSP core include 2K x 16 data RAM, 64K word code and data space, 16 x 16 bit two’s complement

parallel multiplier with 32-bit product, single cycle multiply/accumulate instructions, 36-bit ALU, two 36-bit accumulators,

six-general purpose 16-bit pointer registers, option for up to eight user-defined 16-bit registers, zero overhead looping,

repeat and block-repeat instructions with one nesting level, shifting capability, automatic saturation mode on overflow

while reading content of accumulators, divide and normalize step support.

As noted on Figure 1, the DSP subsystem is supported by two dedicated Pine internal busses called the DSP code bus

and the DSP data bus. All DSP peripherals are connected to the DSP data bus while the code bus is used for just that,

DSP code ROM and RAM. Both the DSP code and data busses are 16-bit for the address and data lines on each bus.

DSP code also enables the DSP core to act as a PCI bus master making it a powerful and flexible audio processing

unit.

DSP Interrupt Controller

The DSP Interrupt Controller is a programmable, priority encoded device that encodes two interrupt signals to the Pine

core. The DSP Interrupt Controller resides on the DSP data bus and is programmed by DSP code. Both sets of

interrupt vectors feature an enable and status bit for each interrupt based device.

DSP Memory Controller

The DSP memory controller provides controls and decodes for the regular DSP data and code RAMs as well as the

code ROMs. The Memory Controller also includes a patch mechanism to allow ROM code to be updated or fixed using

a trapping device.

Game Port

The SAA7780 Game Port interface is designed to emulate the PC-AT based legacy joystick operation as well as

support of a digital joystick mode. The legacy or analog, type of operation is designed to support all legacy software that

uses the original joystick address and the method for resolving the joystick axes positions. The Digital Mode is

designed to reduce the joystick overhead by resolving the joystick position directly and to support applications that use

DirectInput.

The legacy joystick used a one shot multi-vibrator on each of the four joystick potentiometers. These one shots were

set up to deliver a pulse that was proportional to the resistor value of the joystick potentiometers. Software would them

poll the one shots to see if they had been set to the original value. The time it took for each axes to return to the original

value was resolved into a position by the legacy software. The SAA7780 emulates the 558 based one shot circuit to

support legacy games that use the PC-AT joystick. The joystick button values were routed directly to the system bus

where only a decode was required to read the value of the button. Software would poll the buttons as well. All button

and joystick axes data is returned in a single byte wide register.

Game Port Legacy I/O Register

This register is the legacy mode register for the 558 based joystick. Typically, this register is located at legacy address

of 201h. Reads from this register will poll the status of the joystick buttons and are used to resolve the position. Writes

1999 Sep 30

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