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AS2843D-8

Current Mode Controller

Astec Semiconductor => Silicon Link 

AS384x

Current Mode Controller

latch is still fully operative, and the normal termi-

nation of this cycle by the current sense com-

parator will latch the output low until the

over-temperature condition is rectified. Cycling

the power will reset the over-temperature disable

mechanism, or the chip will re-start after cooling

through a nominal hysteresis band.

Section 2 Ð Design Considerations

2.1 Leading edge filter

The current sensed by RS contains a leading

edge spike as shown in Figure 20. This spike is

caused by parasitic elements within the circuit

including the interwinding capacitance of the

power transformer and the recovery characteris-

tics of the rectifier diode(s). The spike, if not prop-

erly filtered, can cause stability problems by

prematurely terminating the output pulse.

A simple RC filter is used to suppress the spike.

The time constant should be chosen such that it

approximately equals the duration of the spike. A

good choice for R1 is 1 k½, as this value is opti-

mum for the filter and at the same time, it simpli-

fies the determination of RSLOPE (Section 2.2). If

the duration of the spike is, for example, 100 ns,

then C is determined by:

Time Constant

C=

(6)

1 kΩ

= 100 ns

1 kΩ

= 100 pF

2.2 Slope compensation

Current-mode controlled converters can experi-

ence instabilities or subharmonic oscillations

Ve

IPK

Ve

IAVG 2

IL2

∆I

IAVG 1

m

2

IL1

∆I'

m

2

T0

D1

D2

T1

(a)

T0

D1

D2

T1

(b)

VCOMP

IL2

IL1

m

=

m

2

/2

IAVG 1 = IAVG 2

m

2

VCOMP

∆I

m

=

m

2

/2

∆I'

m

2

T0

D1

D2

T1

T0

D1

(c)

Figure 22. Slope Compensation

ASTEC Semiconductor

18

D2

T1

(d)

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