PI6C133-03 Просмотр технического описания (PDF) - Pericom Semiconductor
Номер в каталоге
Компоненты Описание
производитель
PI6C133-03 Datasheet PDF : 15 Pages
| |||
PI6C133-03
133 MHz Clock Generation
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788f99o00r1122P3344e55n6677t88i99u00m11223344I55I66/77I88I99I0011P22r1122o33c44e5566s77s88o99r0011s22
Notes:
1. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @1.5V for 3.3V clocks.
2. The PCICLK clock is the Host clock divided by four at Host = 133 MHz. 3V66 clock internal VCO frequency
divided by three for Host = 100 MHz
3. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 Clock is internal VCO frequency divided
by three for Host = 100 MHz
4. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
5. TLOW is measured at 0.4V for all outputs.
6. The time specified is measured from when VDDQ achieves its nominal operating level (typical condition VDDQ = 3.3V)
until the frequency output is stable and operating with in specification.
7. TRISE and TFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA)
JEDEC Specification.
8. The average period over any 1µs period of time is greater than the minimum specified period.
9. Calculated at minimum edge rate(1V/ns) to guarantee 45/55% duty-cycle. Pulsewidth is required to be wider at
faster edge-rate to ensure duty cycle specification is met.
Group Skew and Jitter Limits
Output Group
Pin-Pin
Skew
CPU
175ps
APIC
500ps
48MHz
N/A
3V66
250ps
PCI
500ps
REF
N/A
Cycle-Cycle
Jitter
150ps
250ps
500ps
500ps
500ps
1000ps
Duty Cycle
45/55
45/55
45/55
45/55
45/55
45/55
Nom Vdd
Skew, Jitter
Measure Point
2.5V
1.25V
3.3V
1.5V
Group Offset Limits
Group
Offset
Measurement Loads (Lumped)
Measure Points
CPU to 3V66
0.0-1.5ns CPU Leads
CPU@20pF, 3V66@30pF
CPU@1.25V, 3V66@1.5V
CPU to PCI
1.5-4.0ns CPU Leads
CPU to APIC
1.5-4.0ns CPU Leads
Notes:
1. All offsets are to be measured at rising edges
3V66@30pF, CPU@30pF
CPU@20pF, APIC@20pF
3V66@1.5V, PCI@1.5V
CPU@1.25V, APIC@1.5V
Only offset specifications listed above are guaranteed/tested. The specification is treated as ANY ouput within the
first specified bank to ANY output of the specified bank. Pin-pin skew is implied within offset specification, jitter
is not. Previous offset specifications such as CPU to PCI offset are no longer required.
361
PS8415
07/23/99
Share Link: 