Z87L00 Просмотр технического описания (PDF) - Zilog

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Z87L00

SPREAD SPECTRUM CONTROLLERS

Zilog 

Zilog

Z87000/Z87L00

Spread Spectrum Controllers

Table 22. Bank 2 Register Description

BIAS_ERROR

Bank 2

EXT2

Field

Bit Position

R/W Data

Description

1

BIAS_ERROR_DATA fedcba9876543210

Access to the bias estimate from the AFC loop.

R XXXXh Current bias estimate value

W

No effect

Notes:

BIAS_ERROR_DATA. This value is used to bias the downconverter’s NCO if the USE_CORE_BIAS register field is reset. It is en-

coded as a 2’s complement number. The unit is 125 Hz

.

Table 23. Bank 2 Register Description

RSSI

Field

Bank 2

Bit Position

EXT3

R/W Data

Description

RESERVED

fedcba98-------- R

W

Returns 0

No effect

RSSI_DATA

-------76543210

Access to 8-bit ADC (can be used for RSSI data)

R XXh Returns latest value on 8-bit DAC

W

No effect

Note:

RSSI_DATA. This value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data.

Table 24. Bank 2 Register Description

CORE_BIAS

Field

Bank 2

Bit Position

EXT4

R/W Data

Description

RESERVED

fed------------- R

W

Returns 0

No effect

CORE_BIAS_DATA

---cba9876543210

Stores bias value for correction of downconverter’s

NCO.

R

Returns 0

W xXXXh Updates bias value

Notes:

CORE_BIAS_DATA.This value is used if the USE_CORE_BIAS register field is set. It is encoded as a 2’s complement number.

The unit is 125 Hz.

DS96WRL0501

PRELIMINARY

1-41

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