Z80185 Просмотр технического описания (PDF) - Zilog

Номер в каталоге

Компоненты Описание

производитель

Z80185

SMART PERIPHERAL CONTROLLERS

Zilog 

Zilog

PRELIMINARY

Bit

Upon Reset

R/W

CNTLB0

MPBT MP

Invalid 0

R/W R/W

/CTS/

PS

†

R/W

PE0

0

R/W

Addr 02H

DR SS2 SS1 SS0

0

1

1

1

R/W R/W R/W R/W

Z80185/Z80195

SMART PERIPHERAL CONTROLLERS

General

Divide Ratio

SS, 2, 1, 0

000

001

010

011

100

101

110

111

† /CTS - Depending on the condition of /CTS pin.

PS - Cleared to 0.

PS = 0

(Divide Ratio = 10)

DR = 0 (x16)

DR = 1 (x64)

Ø ÷ 160

Ø ÷ 640

Ø ÷ 320

Ø ÷ 1280

Ø ÷ 640

Ø ÷ 2560

Ø ÷ 1280

Ø ÷ 5120

Ø ÷ 2560

Ø ÷ 10240

Ø ÷ 5120

Ø ÷ 20480

Ø ÷ 10240

Ø ÷ 40960

External Clock (Frequency < Ø)

Clock Source and Speed Select

Divide Ratio

Parity Even or Odd

Clear To Send/Prescale

Multiprocessor

Multiprocessor Bit Transmit

PS = 1

(Divide Ratio = 30)

DR = 0 (x16)

Ø ÷ 480

Ø ÷ 960

Ø ÷ 1920

Ø ÷ 3840

Ø ÷ 7680

Ø ÷ 15360

Ø ÷ 30720

DR = 1 (x64)

Ø ÷ 1920

Ø ÷ 3840

Ø ÷ 7680

Ø ÷ 15360

Ø ÷ 30720

Ø ÷ 61440

Ø ÷ 122880

Figure 24. ASCI Control Register B (Ch. 0)

38

DS971850301

Share Link: